A Universal CLA Adder Generator for SRAM-Based FPGAs

In this paper we present an universal module generator for hierarchical carry lookahead adders of any word length which is suitable for most SRAM-based FPGA architectures. We introduce a generic model of SRAMbased FPGAs taking different configurations of the logic blocks into account. Considering the logical structure of CLA adders we efficiently perform technology mapping including an adaptive structure generation process as well as signal flow driven placement and partitioning which is necessary if the macro exceeds the limitations given by the FPGA's pin or CLB count.